1. Field of the Invention
The present invention relates to a PLL circuit which raises less phase error (offset) in a semiconductor integrated circuit.
2. Description of the Background Art
The higher the speed due to miniaturization of LSI technique, the smaller the allowance for the phase error between system clock and inside the LSI, which improves the frequency of using a PLL circuit for compensating such phase error.
FIG. 14 is a block diagram showing a configuration of a conventional PLL circuit. As shown in FIG. 14, a PLL circuit 20 is configured by a PFD (Phase Frequency Detector; phase comparator) 21, a CP (Charge Pump) 22, an LF (Loop Filter) 23 and a VCO (Voltage Controlled Oscillator) 24. With this configuration, the PLL circuit 20 receives an input clock ICLK which is a reference clock and a return clock RCLK, conducts a phase synchronization process (PLL process) so as to make the input clock ICLK and the return clock RCLK synchronous with each other, and outputs a PLL output OUTP.
The PFD 21 detects a phase difference (time) between the input ICLK and the return clock RCLK and outputs a phase, comparison signal to the CP 22. The CP 22 converts the phase comparison signal to a current value and outputs it to the LF 23. The LF 23 converts the current value obtained from the CP 22 to a voltage value. The VCO 24 outputs a PLL output OUTP which oscillates at a frequency based on the voltage value obtained in the LF 23. This PLL output OUTP returns to the PFD 21 as the return clock RCLK via an external circuit.
FIG. 15 is a timing chart showing a relationship between input clock ICLK and return clock RCLK after synchronization by the PLL circuit. As shown in FIG. 15, the input clock ICLK and the return clock RCLK are completely synchronous with each other with an offset OS being xe2x80x9c0xe2x80x9d.
In the PLL circuit 20, however, asymmetry in the circuit configuration of the respective circuits which generate the input clock ICLK and the return clock RCLK, or unevenness generated in the manufacture process of the semiconductor circuit may cause a phase error between the PFD 21 and the CP 22. Though the former can be improved by eliminating the phase error by improving the asymmetry, it is difficult to improve the latter because it is just like a physical phenomenon.
Therefore, it is difficult to make the phase error completely zero in a PLL circuit of such a conventional configuration, and a small phase error necessarily arises. Though the absolute value of the time of such a phase error has not changed in the past, the allowable range of phase error decreases because the ratio with respect to the clock periodicity which is becoming faster year after year certainly increases, which is getting unignorable situation.
FIG. 16 is a timing chart showing a relationship between input clock ICLK and return clock RCLK after synchronization by the PLL circuit. As shown in FIG. 16, an offset not being xe2x80x9c0xe2x80x9d occurs between the input clock ICLK and the return clock RCLK.
Though the conventional PLL circuit desires perfect synchronization as shown in FIG. 15, there has been a practical problem that an unignorable offset OS not being xe2x80x9c0xe2x80x9d occurs, as shown in FIG. 16.
It is an object of the present invention to provide a PLL circuit in which a phase error is reduced to an ignorable level.
According to the present invention, a PLL circuit includes first and second delay means, a PLL part, and phase difference reducing delay control means. The first delay means delays a reference clock by a first delay time to obtain a delayed reference clock, the second delay means delays a return clock by a second delay time to obtain a delayed return clock, the PLL part receives the delayed reference clock and the delayed return clock and outputs a PLL output so that phases of these clocks are synchronous with each other, a signal in association with the PLL output returns thereto as the return clock, the phase difference reducing delay control means performs a delay means controlling process based on the reference clock and the return clock, and the delay means control process changes at least one of the first and second delay times so that a phase difference between the reference clock and the return clock is reduced.
The phase difference reducing delay control means of the PLL circuit of the present invention can improve a phase error between the input clock and the return clock even when a phase difference occurs between the input clock and the return clock during phase synchronization by the PLL part by executing a delay means controlling process which changes at least one of the first and the second delay times so that the phase difference between the reference clock and the return clock is reduced based on the basis of the reference clock and the return clock.
According to the present invention, the PLL circuit is characterized in that the phase difference reducing delay controlling means includes phase comparing means and delay control means, the phase comparing means compares phases of the reference clock and the return clock to output a phase comparison signal, and the delay controlling means performs the delay means controlling process wherein a degree of advance in phase of the return clock with respect to the input clock is determined based on the phase comparison signal, and first and a second delay control signals are outputted to the first and second delay means, the first and the second delay control signals being such that the instruction contents thereof change in such a direction that a relative delay time of the second delay time to the first delay time increases when a phase advance determination representing that the return clock advances in phase is made, and in such a direction that the relative delay time decreases when a phase delay determination representing that the return clock delays in phase is made.
The delay control means of the PLL circuit can change the above-mentioned relative time in the direction of reducing the phase difference between the delayed input clock and the return clock by outputting the first and the second delay control signals the first and the second delay control signals of which instruction contents change in such a direction that a relative delay time of the second delay time to the first delay time increases when a phase advance determination representing that the return clock advances in phase is made, and in such a direction that the relative delay time decreases when a phase delay determination representing that the return clock delays in phase is made.
According to the present invention, the PLL circuit is characterized in that the phase difference reducing delay control means starts the delay means controlling process after a predetermined time which is not less than a time within which the PLL part is assumed to complete synchronization process of the delayed reference clock and the delayed return clock has elapsed.
The phase difference reducing delay control means of the PLL circuit can improve the phase error without adversely affecting the synchronization process by the PLL part by starting the delay means control process after the synchronization process by the PLL part has completed.
According to the present invention, the PLL circuit further includes a synchronization detecting circuit receives the delayed reference clock and the delayed return clock, detects whether or not these signals have come into synchronization with each other to output a synchronization detection signal, and the phase difference reducing delay control means starts the delay means controlling process after the synchronization detection signal has indicated synchronization of the delayed reference clock and the delayed return clock.
The phase difference reducing delay control means of the PLL circuit can improve the above-mentioned phase error rapidly after completion of synchronization without adversely affecting the synchronization process by the PLL part by starting the delay means control process after the synchronization detecting signal indicates synchronization of the delayed reference clock and the delayed return clock.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.